One approach to the parallel computation of solutions is to use reconfigurable hardware to create custom co-processors to accelerate the algorithm. Reconfigurable computing is based around the use of Field Programmable Gate Arrays (FPGAs) to form co-processors that can be configured to provide custom hardware accelerators. These can exploit parallelism within the problem in a much more thorough way than can be done with uniprocessor or parallel computers using general processors. Recent FPGA devices have tens of millions of programmable logic gates capable of achieving frequencies up to 550MHz, reasonable large on-chip memory and fast I/O resources. The performance of floating point units in FPGAs has increased significantly in recent years, as built-in multipliers have been incorporated, so that floating point units can be operated up to 230MHz. For the right type of application, a reconfigurable computer can rival the expensive parallel computers that are normally used to accelerate computationally expensive algorithms. However, the speed-up achievable depends strongly on the method used to solve the equations, the size of the problem and the domain decomposition method used.

This paper investigates the use of FPGAs to accelerate the finite difference method to solve a three-dimensional Laplace equation. In [1], the authors implemented a solution using fixed-point arithmetic in order to conserve hardware resources. This enabled one entire two-dimensional section of the problem to fit in a single FPGA chip. However, fixed point is suitable only for a restricted class of problems, which have very favorable error propagation characteristics and a very small dynamic range of problem parameters. This paper presents a floating-point implementation, and evaluates the significant differences between the fixed-point and floating-point hardware versions. One consequence of the use of floating point arithmetic is that an entire two-dimensional sub problem will not fit simultaneously inside the FPGA, thus increasing the complexity of hardware design.

The floating-point hardware design can achieve a speed-up of 24 for a single FPGA board (in [1], a speed-up of 30 was achieved for the fixed point version) compared to a software solution. If n FPGA boards are used, it can achieve a speed up of 24n. In this paper, we will analyze the features of the system that limit the speed-up achievable and discuss the future research on FPGA-based reconfigurable computing systems.

1

J. Hu, E.J.C. Stewart, S.F. Quigley, A.H.C. Chan, "FPGA-based reconfigurable computing system for the three-dimensional finite difference solution of the Laplace Equation", in 14th Annual conference of the Association for Computational Mechanics in Engineering (ACME), C.G. Armstrong (ed.), Queen's University of Belfast, Belfast, 2006.

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