Keywords: high performance computing, architectures, solutions.

High Performance Computing (HPC) architectures are a hotly debated issue as the designers of such systems are increasingly facing new challenges while traditional approaches seem to be running out of steam. A few years ago, HPC centers were concerned with the lack of variety of architectures and suspected that a monocultural world would take hold of the HPC market. In a recent discussion on architectures at the International Supercomputing Conference at Dresden [1], hardware vendors stated that it is the diversity of existing architectures that has made it increasingly difficult to make investment decisions when it comes to designing large scale systems. On the other hand, HPC centers are still concerned that they might be running out of options when it comes to procuring for the next generation of systems.

The situation in the field of HPC is now more complicated than it was 10 years ago. IBM recently decided to sell its manufacturing facilities. The step that was widely assumed as a starting point for an exit strategy from the hardware business. At the same time, they made the design for the Power architecture publicly available – giving the market another visible signal for a retreat from the HPC market. These were two steps that followed the decision of IBM to sell its x86 activities to Lenovo – a Chinese vendor that had already taken over when IBM dropped their laptop business. Furthermore, the market has received signals that the highly successful BlueGene line of IBM may not see a follow-on product. With IBM gradually slipping out of sight for HPC, and with the disappearance of vendors like SUN, the HPC market is left with few options – having experienced a decline in the number of stable vendors over the last few years.

Technically HPC is facing the end of a development that used to be called Moore's law [2]. Processor clock frequencies – which carried the main load of speeding up hardware - cannot be further increased. Multi-core processors have become standard. So-called accelerators provide solutions that push the number of cores on a single chip to extremes but leave the users with adapting their codes to a new architecture and a new programming model.

In this paper, we will dive into a number of questions that come up in this context. We will explore the messages that the history of the TOP500 [3] list provides. In more recent editions, we have seen interesting developments that will be important for centers and users alike. We will, furthermore, look into technically new trends that may help to overcome some of the limitations that we face with massively parallel systems. Finally, we will try to explore and evaluate new technologies that might be available to the market in the near future.

[1]

ISC 2014, Dresden, Germany, www.supercomp.de

[2]

G.E. Moore, Cramming more components onto integrated circuits, Electronics, 38(8), 114-117, 1965.

[3]

www.top500.org

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